Non-deterministic latency and jitter issues have arisen with the increased use of commercial multicore processors (MCP) as the hardware platforms for hosting Department of Defense (DoD) systems. Within the civilian world of avionics flight control, an approach to dealing with non-deterministic latency issues arising from interference channels within multicore-based, hard real-time, flight control applications has been documented in the Certification Authorities Software Team (CAST) Position Paper (CAST-32A) on Multi-Core Processors and the Federal Aviation Administration?s report on Assurance of Multicore Processors in Airborne Systems (DOT/FAA/TC-16/51, dated July 2017).
Many, perhaps most, DoD safety-critical systems are not hard real-time. Missing some deadlines can be tolerated and adequately addressed with mitigations such as data time-stamps and checks to discard ?stale? data. As firm or soft real-time systems, performance may degrade, but catastrophic consequences can be prevented. For these systems, the approach used for hard real-time avionics flight control systems is unnecessary and not cost effective.
This paper discusses the mismatch of the CAST-32A approach for firm and soft real-time, non-avionics systems and presents a simpler, more agile, testable approach to MCP risk control based on a long-used criterion from the realm of network management.
